1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly to a method for fabricating a capacitor device with BiCMOS processes and the capacitor device formed thereby.
2. Description of the Prior Art
Recently, capacitor devices have become principal components of many semiconductor integrated circuits. For example, a stacked capacitor is used in a dynamic random access memory (DRAM), or a capacitor having two electrodes and a dielectric layer is applied in a mix-logic/analog circuit.
Referring to FIG. 1, a conventional capacitor used in a mix-logic/analog circuit is schematically depicted in a cross-sectional view. The circuit, including a BiCMOS device, is formed upon a silicon substrate 10 of a P-type conductivity, in which a plurality of field oxides FOX are formed to isolate a plurality of active regions of the device. A CMOS region 11 composed of an NMOS transistor 110 and a PMOS transistor 111 on a P-well and an N-well having a gate G1, a source S1, a drain D1, and a gate G2, a source S2, a drain D2, respectively, is formed by traditional processes. An NPN bipolar transistor 12 formed adjacent to the CMOS region 11 includes a collector 120, a base 121, a base contact 123, an emitter 122, and an emitter contact 124. Adjacent to the bipolar transistor 12 is a poly to poly electrodes capacitor 13 composed of a bottom electrode (a polysilicon layer) 131, a polysilicon layer 132 for decreasing the resistance of the junction, a dielectric layer (a silicon dioxide layer) 133, and an upper electrode (a polysislicon layer) 134. Further, in order to increase the conductivity of the bottom electrode 131, an ion implantation or in-situ doped implantation is used to implant Arsenic ions or Phosphorous ions into the polysilicon layer 131. An N-type conductivity layer is therefore formed.
As described above, a capacitor basically has two electrodes (conducting plates) spaced by an insulator (a silicon dioxide layer). As well known by those persons skilled in this field, the most important parameters effecting the charges stored in the capacitor are the dielectric constant, thickness of the insulator, and the area of the capacitor plates. However, the capacitor with this structure described above suffers from depletion. In order to prevent the occurrence of the depletion issue, the bottom electrode is therefore doped with a high concentration ions. This will increase the thickness of the silicon dioxide layer (insulator) formed by oxidation of a thermal cycle thereafter. According to the calculation of the capacitance C, wherein C equals to the voltage drop of the capacitor divided by the thickness of the capacitor (C=xcex5/d), the capacitance is reduced due to the increment of the thickness of the insulator. Further, the performance of the device is effected.
In addition, the process include two steps of forming polysilicon layers. The time and the cost for fabricating the two layers is therefore increased.
Accordingly, an object of the present invention is to provide a simple and inexpensive method for fabricating a capacitor device with BiCMOS processes wherein the dielectric layer of the capacitor formed therein is thin.
The other object of the present invention is to provide a capacitor device formed in an epitaxy layer in which a doping region is formed to be an electrode of the capacitor. Therefore, neither time nor the cost is increased. Moreover, the capacitor formed therein has high capacitance and good performance.
To attain the first object of the present invention, a method for fabricating a capacitor device with BiCMOS processes on a semiconductor substrate is provided. The method comprises the following steps. First, a first buried layer and a second buried layer are formed in the semiconductor substrate. Subsequently, an epitaxy layer is formed above the semiconductor substrate, then three wells and a collector region are formed in the epitaxy layer, wherein two of the three wells form a CMOS transistor region, and the other well is a bottom electrode of the capacitor device. Additionally, the collector region and the bottom electrode are in contact with the two buried layers, respectively. After forming an oxide layer over the three wells to be a gate oxide layer of the CMOS transistor and the dielectric layer of the capacitor device, a base region adjacent to the collector region is formed. Afterward, a polysilicon layer is formed on the three wells and the base region to form gate electrodes of the CMOS transistor, an upper electrode of the capacitor device, and a base contact of the base region. Subsequently, source/drain regions and a base region are formed adjacent to the region below the gates of the CMOS transistor and adjacent to the region below the base contact, respectively. In addition, an emitter region is formed in the base region.
It is noted that the dielectric layer is formed on the epitaxy layer by oxidation, directly. Therefore, the thickness of the dielectric layer is thinner than in the conventional art by means of adjusting the ion concentration of the well region (bottom electrode). According to the formula: C=xcex5/d mentioned before, decreased xe2x80x9cdxe2x80x9d leads to increased xe2x80x9cCxe2x80x9d. That is: the capacitance of the capacitor according to the present invention is higher than that of the prior art. In addition, the capacitor device is formed with BiCMOS processes, additional steps are not added in the processes. Neither the cost nor the time is increased.
Furthermore, the device described above may contact other devices by the following steps. First, an insulating layer, for example, a boro-phospho-silicate-glass (BPSG) layer is formed above the epitaxy layer, then a plurality of openings are formed in the insulating layer to expose the polysilicon layer, source and drain regions, the collector region, and the base contact. Subsequently, a plurality of plugs are formed in the openings to contact with other devices.
To attain the second object of the present invention, a capacitor device formed with BiCMOS processes on a semiconductor substrate is provided, comprising: a buried layer formed in the semiconductor; an epitaxy layer formed over the semiconductor; a bipolar junction transistor formed in the epitaxy layer having a collector region; a CMOS transistor having a gate oxide and a gate electrode; a well region formed with the collector region in the epitaxy layer and contacting with the buried layer, said well region being a bottom electrode of the capacitor device; an oxide layer formed with the gate oxide on the epitaxy layer over the well, said oxide layer being a dielectric layer of the capacitor device; and a conducting layer formed with the gate electrode on the oxide layer, said conducting layer being an upper electrode of the capacitor device.